Many integrated circuit devices require internal voltage levels that are not supplied directly from external circuit nodes. State of the art dynamic random access memories (DRAMs) for example are designed with internal voltage pump circuits to generate an elevated supply voltage for use in turning on n-channel memory cell access devices to allow a full Vcc signal level to pass through the access device into or out of a memory cell. The elevated supply voltage may also be used in output buffer circuits to allow the use of n-channel pull-up devices which provide a CMOS output buffer which is less susceptible to latch-up. The elevated supply voltage is required for controlling the gate node of n-channel transistors in order to prevent a threshold voltage (Vt) drop in logic high signals passed through the transistor.
It is also desirable in DRAM devices to generate a slightly negative internal supply voltage to bias the device substrate below GND potential. The negative supply may also be used to control p-channel transistor gates to allow the p-channel transistors to effectively pass logic low signals.
Typical DRAM devices utilize multiple voltage pump circuits comprising oscillators, coupling capacitors and diodes to generate these internal voltage supplies. Capacitor bootstrap circuits are also comnmonly used in output buffer circuits to generate above Vcc gate driving voltages for n-channel pull-up transistors. Simple voltage pump circuits are not very efficient. State of the art DRAMs require significant amounts of current to drive large numbers of memory array access devices simultaneously. To meet certain refresh timing requirements, multiple word lines may be driven simultaneously, requiring thousands of access devices to be activated with the elevated supply voltage. Further complicating the elevated voltage generation circuit design is the fact that advanced CMOS processes require internal device circuitry to operate at reduced supply voltages. These low level internal operating voltages have led to requirements for reduced Vcc supply input voltages. Prior art DRAM voltage pump circuits tend to fail at low Vcc levels, or become so inefficient that they are impractical. A need remains for a high efficiency voltage generation circuit which may be fabricated within large scale CMOS integrated circuits that will operate at Vcc levels below three volts, and eventually below one volt Vcc.